advance information this data sheet states amd?s current technical specifications regarding the products described herein. this data sheet may be revised by subsequent versions or modifications due to changes in technical specifications. publication# 25263 rev: a amendment/ +4 issue date: april 26, 2002 refer to amd ? swebs i te (www.amd.com) for the latest i nformat i on. am29lv256m 256 megabit (16 m x 16-bit/32 m x 8-bit) mirrorbit ? 3.0 volt-only uniform sector flash memory with versatilei/o ? control distinctive characteristics architectural advantages single power supply operation ? 3 volt read, erase, and program operations versatilei/o ? control ? device generates and tolerates voltages on ce# and dq i/os as determined by the voltage on the v io pin; operates from 1.65 to 3.6 v manufactured on 0.23 m mirrorbit process technology secsi ? (secured silicon) sector region ? 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random electronic serial number, accessible through a command sequence ? may be programmed and locked at the factory or by the customer flexible sector architecture ? five hundred twelve 32 kword (64 kbyte) sectors compatibility with jedec standards ? provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection minimum 100,000 erase cycle guarantee per sector 20-year data retention at 125 c performance characteristics high performance ? 90 ns access time ? 25 ns page read times ? 0.4 s typical sector erase time ? 5.9 ? typical write buffer word programming time: 16-word/32-byte write buffer reduces overall programming time for multiple-word updates ? 4-word/8-byte page read buffer ? 16-word/32-byte write buffer low power consumption (typical values at 3.0 v, 5 mhz) ? 30 ma typical active read current ? 50 ma typical erase/program current ? 1 a typical standby mode current package options ? 56-pin tsop ? 64-ball fortified bga software & hardware features software features ? program suspend & resume: read other sectors before programming operation is completed ? erase suspend & resume: read/program other sectors before an erase operation is completed ? data# polling & toggle bits provide status ? unlock bypass program command reduces overall multiple-word or byte programming time ? cfi (common flash interface) compliant: allows host system to identify and accommodate multiple flash devices hardware features ? sector group protection: hardware-level method of preventing write operations within a sector group ? temporary sector unprotect: v id -level method of changing code in locked sectors ? wp#/acc input accelerates programming time (when high voltage is applied) for greater throughput during system production. protects first or last sector regardless of sector protection settings ? hardware reset input (reset#) resets device ? ready/busy# output (ry/by#) detects program or erase cycle completion
2 am29lv256m april 26, 2002 advance information general description the am29lv256m is a 256 mbit, 3.0 volt single power supply flash memory devices organized as 16,777,216 words or 33,554,432 bytes. the device has a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the byte# input. the device can be programmed either in the host system or in standard eprom programmers. an access time of 90, 100, 110, or 120 ns is available. note that each access time has a specific operating voltage range (v cc ) and an i/o voltage range (v io ), as specified in the product selector guide and the order- ing information sections. the device is offered in a 56-pin tsop or 64-ball fortified bga package. each device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. each device requires only a single 3.0 volt power supply for both read and write functions. in addition to a v cc input, a high-voltage accelerated program ( wp#/ acc) input provides shorter programming times through increased current. this feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. the device is entirely command set compatible with the jedec single-power-supply flash standard . commands are written to the device using standard microprocessor write timing. write cycles also inter- nally latch addresses and data needed for the pro- gramming and erase operations. the sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. device programming and erasure are initiated through command sequences. once a program or erase oper- ation has begun, the host system need only poll the dq7 (data# polling) or dq6 (toggle) status bits or monitor the ready/busy# (ry/by#) output to deter- mine whether the operation is complete. to facilitate programming, an unlock bypass mode reduces com- mand sequence overhead by requiring only two write cycles to program data instead of four. the versatilei/o? (v io ) control allows the host sys- tem to set the voltage levels that the device generates and tolerates voltages on the ce# and dq i/os to the same voltage level that is asserted on the v io pin. this allows the device to operate in a 1.8 v or 3 v system environment as required. hardware data protection measures include a low v cc detector that automatically inhibits write opera- tions during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. this can be achieved in-system or via programming equipment. the erase suspend/erase resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. the program suspend/program resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the pro- gram operation. the hardware reset# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the host system to read boot-up firmware from the flash memory device. the device reduces power consumption in the standby mode when it detects specific voltage levels on ce# and reset#, or when addresses have been stable for a specified period of time. the secsi ? (secured silicon) sector provides a 128-word/256-byte area for code or data that can be permanently protected. once this sector is protected, no further changes within the sector can occur. the write protect (wp# /acc ) feature protects the first or last sector by asserting a logic low on the wp# pin. amd mirrorbit flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effec- tiveness. the device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. the data is programmed using hot electron injection.
april 26, 2002 am29lv256m 3 advance information product selector guide block diagram part number am29lv256m speed option v cc = 3.0 ? 3.6 v 90r (v io = 3.0 ? 3.6 v) v cc = 2.7 ? 3.6 v 101 (v io = 2.7 ? 3.6 v) 112 (v io = 1.65 ? 3.6 v) 120 (v io = 1.65 ? 3.6 v) max. access time (ns) 90 100 110 120 max. ce# access time (ns) 90 100 110 120 max. page access time (t pacc )25304040 max. oe# access time (ns) 25 30 40 40 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss v io we# wp#/acc byte# ce# oe# stb stb dq0 ? dq15 (a-1) sector switches ry/by# reset# data latch y-gating cell matrix address latch a23 ? a0
4 am29lv256m april 26, 2002 advance information connection diagrams 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a23 a22 a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# a21 wp#/acc ry/by# a18 a17 a7 a6 a5 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 nc nc a16 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 23 24 25 26 27 28 a4 a3 a2 a1 nc nc 34 33 32 31 30 29 oe# v ss ce# a0 nc v io 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a23 a22 a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# a21 wp#/acc ry/by# a18 a17 a7 a6 a5 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 nc nc a16 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 23 24 25 26 27 28 a4 a3 a2 a1 nc nc 34 33 32 31 30 29 oe# v ss ce# a0 nc v io 56-pin standard tsop 56-pin reverse tsop
april 26, 2002 am29lv256m 5 advance information connection diagrams note: the fbga package pinout configuration shown is preliminary. the ball count and package physical dimensions have not yet been determined. contact amd for further information. special package handling instructions special handling is required for flash memory products in molded packages (tsop, bga, plcc, pdip, ssop). the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged periods of time. a2 c2 d2 e2 f2 g2 h2 a3 c3 d3 e3 f3 g3 h3 a4 c4 d4 e4 f4 g4 h4 a5 c5 d5 e5 f5 g5 h5 a6 c6 d6 e6 f6 g6 h6 a7 c7 d7 e7 f7 g7 h7 dq15/a-1 v ss byte# a16 a15 a14 a12 a13 dq13 dq6 dq14 dq7 a11 a10 a8 a9 v cc dq4 dq12 dq5 a19 a21 reset# we# dq11 dq3 dq10 dq2 a20 a18 wp#/acc ry/by# dq9 dq1 dq8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a3 a1 c1 d1 e1 f1 g1 h1 nc nc v io nc nc nc nc nc a8 c8 b2 b3 b4 b5 b6 b7 b1 b8 d8 e8 f8 g8 h8 nc nc nc v ss v io a23 a22 nc 64-ball fortified bga top view, balls facing down
6 am29lv256m april 26, 2002 advance information pin description a23 ? a0 = 24 address inputs dq14 ? dq0 = 15 data inputs/outputs dq15/a-1 = dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) ce# = chip enable input oe# = output enable input we# = write enable input wp#/acc = hardware write protect input; acceleration input reset# = hardware reset pin input byte# = selects 8-bit or 16-bit mode ry/by# = ready/busy output v cc = 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v io = output buffer power v ss = device ground nc = pin not connected internally logic symbol 24 16 or 8 dq15 ? dq0 (a-1) a23 ? a0 ce# oe# we# reset# ry/by# wp#/acc v io byte#
april 26, 2002 am29lv256m 7 advance information ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the following: valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. am29lv256m h 90r pc i temperature range i = industrial ( ? 40 c to +85 c) package type e = 56-pin thin small outline package (tsop) standard pinout (ts 056) f = 56-pin thin small outline package (tsop) reverse pinout (tsr056) pc = 64-ball fortified ball grid array ( f bga), 12 x 18 mm, 1.0 mm pitch (package name tbd) speed option see product selector guide and valid combinations sector architecture and sector write protection (wp# = v il ) h = uniform sector device, highest address sector protected l = uniform sector device, lowest address sector protected device number/description am29lv256mh/l 256 megabit (16 m x 16-bit/32 m x 8-bit) mirrorbit uniform sector flash memory with versatileio ? control 3.0 volt-only read, program, and erase valid combinations for tsop package speed( ns) v io range v cc range am29lv256mh90r, am29lv256ml90r ei, fi 90 3.0 ? 3.6 v 3.0 ? 3.6 v am29lv256mh101, am29lv256ml101 100 2.7 ? 3.6 v 2.7 ? 3.6 v am29lv256mh112, am29lv256ml112 110 1.65 ? 3.6 v am29lv256mh120, am29lv256ml120 120 1.65 ? 3.6 v valid combinations for fortified bga package speed (ns) v io range v cc range order number package marking am29lv256mh90r, am29lv256ml90r pci package marking tbd i 90 3.0 ? 3.6 v 3.0 ? 3.6 v am29lv256mh101, am29lv256ml101 100 2.7 ? 3.6 v 2.7 ? 3.6 v am29lv256mh112, am29lv256ml112 110 1.65 ? 3.6 v am29lv256mh120, am29lv256ml120 120 1.65 ? 3.6 v
8 am29lv256m april 26, 2002 advance information physical dimensions ts056/tsr056 ? 56-pin standard/reverse thin small outline package (tsop) notes: 1 controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982.) 2 pin 1 identifier for standard pin out (die up). 3 pin 1 identifier for reverse pin out (die down), ink or laser mark. 4 to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. 5 dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15 mm per side. 6 dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08 mm total in excess of b dimension at max material condition. minimum space between protrusion and an adjacent lead to be 0.07 mm. 7 these dimesions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 8. lead coplanarity shall be within 0.10 mm as measured from the seating plane. 9 dimension "e" is measured at the centerline of the leads. 3160\38.10a mo-142 (b) ec ts/tsr 56 nom. --- --- 1.00 1.20 0.15 1.05 max. --- min. 0.95 0.20 0.23 0.17 0.22 0.27 0.17 --- 0.16 0.10 --- 0.21 0.10 20.00 20.20 19.90 14.00 14.10 13.90 0.60 0.70 0.50 3? 5? 0? --- 0.20 0.08 56 18.40 18.50 18.30 0.05 0.50 basic e r b1 jedec package symbol a a2 a1 d1 d c1 c b e l n o
april 26, 2002 am29lv256m 9 advance information physical dimensions laa064 ? 64-ball fortified ball grid array ( f bga) 12 x 18 mm package tbd
10 am29lv256m april 26, 2002 advance information revision summary revision a (august 3, 2001) initial release as abbreviated advance information data sheet. revision a+1 (september 12, 2001) ordering information changed package part number designation from wh to pc. physical dimensions added the ts056 and laa064 packages. revision a+2 (october 3, 2001) global corrected title from 64 mbit to 256 mbit. added 120 ns speed option. distinctive characteristics secsi ? (secured silicon) sector region: corrected 64-byte to 256-byte. connection diagram modified fbga ball grid to an 8 x 8 ball matrix. changed rfu (reserved for future use) balls to nc (no connection). ordering information changed operating voltage range on 90 ns speed op- tion to 3.0 3.6 v. pin description added a-1 description. revision a+3 (march 25, 2002) distinctive characteristics clarified description of enhanced versatileio control. physical dimensions added drawing that shows both ts056 and tsr056 specifications. revision a+4 (april 26, 2002) global the laa064 (13 x 11 mm fortified bga) package has been removed. a 12 x 18 fortified bga package will be offered in its place. distinctive characteristics deleted enhanced from versatileio and mofified decscription. trademarks copyright ? 2002 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are registered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies .
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